?002 fairchild semiconductor corporation rfp70n03, rf1s70n03, RF1S70N03SM rev. c rfp70n03, rf1s70n03, RF1S70N03SM 70a, 30v, 0.010 ohm, n-channel power mosfets these n-channel power mosfets are manufactured using the megafet process. this process, which uses feature sizes approaching those of lsi integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. they were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. these transistors can be operated directly from integrated circuits. formerly developmental type ta49025. features 70a, 30v ? ds(on) = 0.010 ? temperature compensating pspice model peak current vs pulse width curve uis rating curve (single pulse) 175 o c operating temperature related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging jedec to-220ab jedec to-263ab jedec to-262aa ordering information part number package brand rfp70n03 to-220ab rfp70n03 rf1s70n03 to-262aa f1s70n03 RF1S70N03SM to-263ab f1s70n03 note: when ordering, use the entire part number. add the suf? 9a to obtain the to-263ab variant in tape and reel, e.g., RF1S70N03SM9a d g s drain (flange) source drain gate drain (flange) gate source drain source gate drain (flange) data sheet january 2002
?002 fairchild semiconductor corporation rfp70n03, rf1s70n03, RF1S70N03SM rev. c absolute maximum ratings t c = 25 o c, unless otherwise speci?d units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 70 200 a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figure 5 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 1.0 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 10) 30 - - v gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 9) 2 - 4 v zero gate voltage drain current i dss v ds = 30v, v gs = 0v - - 1 a v ds = 30v, v gs = 0v, t c = 150 o c--50 a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance r ds(on) i d = 70a, v gs = 10v (figure 8) - - 0.010 ? turn-on time t on v dd = 15v, i d ? 70a, r l = 0.214 ? , v gs = 10v, r gs = 2.5 ? - - 80 ns turn-on delay time t d(on) -20-ns rise time t r -20-ns turn-off delay time t d(off) -40-ns fall time t f -25-ns turn-off time t off - - 125 ns total gate charge q g(tot) v gs = 0v to 20v v dd = 24v, i d ? 70a, r l = 0.343 ? i g(ref) = 1.0ma (figure 12) - 215 260 nc gate charge at 10v q g(10) v gs = 0v to 10v - 120 145 nc threshold gate charge q g(th) v gs = 0v to 2v - 6.5 8.0 nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 11) - 3300 - pf output capacitance c oss - 1750 - pf reverse transfer capacitance c rss - 750 - pf thermal resistance junction to case r jc (figure 3) - - 1.0 o c/w thermal resistance junction to ambient r ja to-220, to-263 - - 62 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 70a - - 1.5 v reverse recovery time t rr i sd = 70a, di sd /dt = 100a/ s - - 125 ns rfp70n03, rf1s70n03, RF1S70N03SM
?002 fairchild semiconductor corporation rfp70n03, rf1s70n03, RF1S70N03SM rev. c typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area note: refer to application notes an9321 and an9322. figure 5. unclamped inductive switching capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 0 t c , case temperature ( o c) 10 20 30 40 50 60 70 80 25 50 75 100 125 150 175 i d , drain current (a) 10 -5 z jc , normalized thermal impedance t 1 , rectangular pulse duration (s) 10 -4 10 -3 10 -2 10 -1 10 -0 10 1 10 -2 10 -1 10 0 single pulse 0.01 0.5 0.2 0.1 0.05 0.02 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 300 100 10 1 1 10 50 v ds , drain to source voltage (v) operation in this area may be limited by r ds(on) v dss(max) = 30v 100 s 1ms 10ms 100ms dc i d , drain current (a) t c = 25 o c t j = max rated single pulse 300 i dm 100 0.01 10 0.10 t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l) (i as )/(1.3 x rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r) ln [(i as x r)/(1.3 x rated bv dss - v dd ) +1] i as , avalanche current (a) 110 rfp70n03, rf1s70n03, RF1S70N03SM
?002 fairchild semiconductor corporation rfp70n03, rf1s70n03, RF1S70N03SM rev. c figure 6. saturation characteristics figure 7. transfer characteristics figure 8. normalized drain to source on resistance vs junction temperature figure 9. normalized gate threshold voltage vs junction temperature figure 10. normalized drain to source breakdown voltage vs junction temperature figure 11. capacitance vs drain to source voltage typical performance curves (continued) v ds , drain to source voltage (v) 0 1.5 3.0 4.5 6.0 7.5 i d , drain current (a) 0 40 80 120 160 200 v gs = 7v v gs = 6v v gs = 5v v gs = 4v v gs = 8v v gs = 10v pulse duration = 80 s t c = 25 o c duty cycle = 0.5% max v gs , gate to source voltage (v) 0246810 drain current (a) 0 40 80 120 160 200 25 o c -55 o c 175 o c pulse duration = 80 s duty cycle = 0.5% max v dd = 15v 2.0 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source pulse duration = 80 s on resistance v gs = 10v, i d = 70a duty cycle = 0.5% max 2.0 1.6 1.2 0.8 0 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized 0.4 gate threshold voltage v gs = v ds ,i d = 250 a 2.0 1.6 1.2 0.4 0 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source 0.8 breakdown voltage i d = 250 a 0 0 5 10 15 20 25 1000 2000 3000 5000 6000 7000 4000 c, capacitance (pf) v ds , drain to source voltage (v) c iss c oss c rss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss = c ds + c gd rfp70n03, rf1s70n03, RF1S70N03SM
?002 fairchild semiconductor corporation rfp70n03, rf1s70n03, RF1S70N03SM rev. c note: refer to application notes an7254 and an7260. figure 12. gate charge waveforms for constant gate current test circuits and waveforms figure 13. unclamped energy test circuit figure 14. unclamped energy waveforms figure 15. switching time test circuit figure 16. switching waveforms typical performance curves (continued) 30.0 22.5 15.0 7.5 0 10.0 7.5 5.0 2.5 0 t, time ( s) 20 i g ref () i g act () --------------------- 80 i g ref () i g act () --------------------- v ds , drain source voltage (v) v gs , gate source voltage (v) v dd = bv dss v dd = bv dss 0.75bv dss 0.50bv dss 0.25bv dss 0.75bv dss 0.50bv dss 0.25bv dss r l = 0.43 ? i g(ref) = 3.0ma v gs = 10v t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 rfp70n03, rf1s70n03, RF1S70N03SM
?002 fairchild semiconductor corporation rfp70n03, rf1s70n03, RF1S70N03SM rev. c figure 17. gate charge test circuit figure 18. gate charge waveform test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 rfp70n03, rf1s70n03, RF1S70N03SM
?002 fairchild semiconductor corporation rfp70n03, rf1s70n03, RF1S70N03SM rev. c pspice electrical model .subckt rfp70n03 2 1 3 ; rev 9/16/92 * nom temp = 25 o c ca 12 8 6.09e-9 cb 15 14 6.05e-9 cin 6 8 3.40e-9 dbody 7 5 dbdmod dbreak 5 11 dbkmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 35.4 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evto 20 6 18 8 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 3.10e-9 lsource 3 7 1.82e-9 mos1 16 6 8 8 mosmod m=0.99 mos2 16 21 8 8 mosmod m=0.01 rbreak 17 18 rbkmod 1 rdrain 5 16 rdsmod 30.7e-6 rgate 9 20 0.890 rin 6 8 1e9 rsource 8 7 rdsmod 3.92e-3 rvto 18 19 rvtomod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 8 19 dc 1 vto 21 6 0.605 .model dbdmod d (is=7.91e-12 rs=3.87e-3 trs1=2.71e-3 trs2=2.50e-7 cjo=4.84e-9 tt=4.51e-8) .model dbkmod d (rs=3.9e-2 trs1=1.05e-4 trs2=3.11e-5) .model dplcapmod d (cjo=4.8e-9 is=1e-30 n=10) .model mosmod nmos (vto=3.46 kp=47 is=1e-30 n=10 tox=1 l=1u w=1u) .model rbkmod res (tc1=8.46e-4 tc2=-8.48e-7) .model rdsmod res (tc1=2.23e-3 tc2=6.56e-6) .model rvtomod res (tc1=-3.29e-3 tc2=3.49e-7) .model s1amod vswitch (ron=1e-5 roff=0.1 von=-8.35 voff=-6.35) .model s1bmod vswitch (ron=1e-5 roff=0.1 von=-6.35 voff=-8.35) .model s2amod vswitch (ron=1e-5 roff=0.1 von=-2.0 voff=3.0) .model s2bmod vswitch (ron=1e-5 roff=0.1 von=3.0 voff=-2.0) .ends note: for further discussion of the pspice model consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; written by william j. hepp and c. frank wheatley. 10 dplcap rdrain dbreak ldrain drain source lsource dbody rbreak rvto vbat + - 19 it rsource ebreak mos2 eds egs rin cin vto esg s1a s2a s2b s1b cb ca evto rgate gate lgate 5 2 18 17 7 11 21 8 6 16 20 9 1 12 15 14 13 13 8 14 13 + - + - + - + - + - + - mos1 3 6 8 5 8 18 8 6 8 17 18 rfp70n03, rf1s70n03, RF1S70N03SM
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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